Multi-user Full-Duplex Single Cell Demonstration
Multi-user Full-duplex single cell demonstration: This work was performed in close collaboration among University of Edinburgh, Heriot Watt University, NIT Trichy, University of Manchester and IIT Indore and was supported by the British Council with the grant "Full Duplex and Cognitive Radio Architectures for Spectrally Efficient Communications ((UGC -UKIERI 2016-17-058)" and The Engineering Physical Science Research Council (UK) with the grant "A Unified Multiple Access Framework for Next Generation (EP/P009670/1)".
Analog Cancellation:
The analog cancellation is done by using power splitter/combiner and fixed attenuator. The Krytar 2-way power divider is used for dividing the transmitted signal into two same phase signals. The first signal is fed to antenna for transmission through air and the other signal is fed to Krytar 2-way power combiner through attenuator and a cable for SI cancellation. In this prototype, passive-suppression method is used for SI cancellation as the length of delay (cable length) and gain of attenuator (Mini-Circuits 30 dB) are fixed.
Digital Cancellation:
The digital SI cancellation of the residual SI is performed using Ettus Research USRP X310 with UBX 160 daughterboard and LabVIEW Communication System Design Suite 3.0. All baseband signal processing of digital cancellation is done on LabVIEW Communication System Design Suite 3.0. USRP X310 is a high-performance, scalable software defined radio platform for developing and deploying wireless communication system. The maximum transmit output power of X310 is +20 dBm. The UBX 160 covers frequencies from 10 MHz to 6 GHz with up to 160 MHz bandwidth in the transmitter chain and 84 MHz in the receiver chain. The X310 has a large user programmable Kintex-7 FPGA for developers to incorporate DSP blocks. The X310 has 14 bit 200 MS/s ADC and 16 bit 800 MS/s DAC. The baseband samples are transferred to/from host PC from/to USRP with the help of 10 gigabit Ethernet PCIe adapter card and SFP+ cable. VERT 2450 vertical omnidirectional antennas are used for transmission and reception of over-the-air signal.
Experimental set-up and demonstration:
The prototype of FD NOMA communication in which FD is performed at the BS. The set-up consists of 1 HD UL user and 2 HD DL users. The BS communicates with DL1 and DL2 through power domain NOMA. DL1 is the weak (near) user while DL2 is the strong (far) user. IEEE 802.11a standard is implemented which is based on orthogonal frequency division multiplexing (OFDM) with fast Fourier transform (FFT) size of 64 and cyclic prefix (CP) is 16. IEEE 802.11a is chosen because its maximum transmit power is same as the USRP used in this demonstration which is +20 dBm. BS transmits a composite signal of binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) to DL1 and DL2 respectively at 2.45 GHz with 5 MHz bandwidth. UL user transmits QPSK modulated signal to BS at the same frequency, same bandwidth, and same time slot. The data transmission is in the form of packet in which each packet has short training field (STF) consisting of 2 OFDM symbols, long training field (LTF) consisting of 2 OFDM symbols, 1 SIGNAL field consisting of 1 OFDM symbol, and payload consisting of 30 OFDM symbols. STF is used for frame detection, and coarse timing and frequency offset estimation. LTF is used for fine timing and frequency offset estimation, and channel estimation. SIGNAL field consists the information about the decoding of payload. In this experiment 15 packets are transmitted in a burst. The LTF, STF, and SIGNAL field are BPSK modulated.
At the BS, the physical layer of IEEE 802.11a is implemented on Host-PC where the payload of each packet is generated as follows: the two sequences of transmitted bits are encoded by Bose-Chaudhuri-Hocquenghem (BCH) code of parameter n (block length) =15, k (number of parity check digits) =7, and t (error correcting bits) =2. Then, the first sequence of encoded bits is BPSK modulated followed by OFDM modulator with FFT size of 64 and CP of 16. The second sequence of encoded bits is QPSK modulated followed by OFDM modulator with FFT size of 64 and CP of 16. The two sequences after OFDM are scaled by α and combined to give one composite baseband signal. This baseband signal is sent to USRP using 10 gigabit Ethernet PCIe adapter card and SFP+ cable. The samples received by the USRP is converted to analog signal using DAC. It upconverts the signal to 2.45 GHz with I/Q rate of 5 MHz and is fed to the 2-way power splitter which is connected with the USRP as shown in the demo. One output of the power splitter is connected with antenna which transmits the signal over-the-air and another output is connected with the input of power combiner at the receiver of same BS USRP through fixed attenuator and cable.
At the BS receiver, the signal is received through two paths. One is through over-the-air and received by antenna at 2.45 GHz which is connected with one input of power combiner. Another input of power combiner at the receiver is connected with cable as shown in the demo. The length of the cable and the gain of the attenuator are adjusted such that the signals received at the inputs of power combiner should have equal strength and opposite phase: the output of the power combiner gives the SI cancelled signal after analog cancellation. The signal coming from the power combiner is fed to USRP where the signal is down converted to baseband and IQ samples are generated by using ADC which is then sent to the Host-PC. In the Host-PC, first the packet detection is performed by using STF followed by channel estimation and carrier frequency offset estimation (CFO) by using LTF. The channel estimation is performed before UL user's transmission and this estimated channel is used for decoding the remaining packets in the presence of UL user transmission. The CFO compensated samples are subtracted by the convolution of the estimated channel and the transmitted OFDM symbols, and the subtraction gives the residual SI. The receiver of BS is intended to receive the UL user transmitted signal and hence the residual SI acts as interference to the UL user communication.
For the UL user, transmit bits are encoded by BCH code of same parameter as used in BS transmission. Then the encoded bits are QPSK modulated followed by OFDM modulator. The baseband I/Q samples generated by OFDM modulator in Host-PC is sent to the USRP. The samples received by USRP is converted to analog signal using DAC, upconverted to 2.45 GHz with I/Q rate of 5 MHz. For DL2 user, the antenna receives the signal at 2.45 GHz and feeds to the USRP in which the signal is down converted to baseband and generates IQ samples by using ADC and sends to the Host-PC. The signal received by the DL2 user also contains DL1 user's signal and UL user's signal. The DL2 decodes its data by treating other signal as interference. Similarly, the signal received by DL1 user's signal is the combination of its own signal, DL2 user's signal and UL signal. Since the signal received by the DL1 user is dominated by DL2 user's signal, the DL1 user first decodes the DL2 user's signal and then performs SIC and finally decodes its own data.
Analog Cancellation:
The analog cancellation is done by using power splitter/combiner and fixed attenuator. The Krytar 2-way power divider is used for dividing the transmitted signal into two same phase signals. The first signal is fed to antenna for transmission through air and the other signal is fed to Krytar 2-way power combiner through attenuator and a cable for SI cancellation. In this prototype, passive-suppression method is used for SI cancellation as the length of delay (cable length) and gain of attenuator (Mini-Circuits 30 dB) are fixed.
Digital Cancellation:
The digital SI cancellation of the residual SI is performed using Ettus Research USRP X310 with UBX 160 daughterboard and LabVIEW Communication System Design Suite 3.0. All baseband signal processing of digital cancellation is done on LabVIEW Communication System Design Suite 3.0. USRP X310 is a high-performance, scalable software defined radio platform for developing and deploying wireless communication system. The maximum transmit output power of X310 is +20 dBm. The UBX 160 covers frequencies from 10 MHz to 6 GHz with up to 160 MHz bandwidth in the transmitter chain and 84 MHz in the receiver chain. The X310 has a large user programmable Kintex-7 FPGA for developers to incorporate DSP blocks. The X310 has 14 bit 200 MS/s ADC and 16 bit 800 MS/s DAC. The baseband samples are transferred to/from host PC from/to USRP with the help of 10 gigabit Ethernet PCIe adapter card and SFP+ cable. VERT 2450 vertical omnidirectional antennas are used for transmission and reception of over-the-air signal.
Experimental set-up and demonstration:
The prototype of FD NOMA communication in which FD is performed at the BS. The set-up consists of 1 HD UL user and 2 HD DL users. The BS communicates with DL1 and DL2 through power domain NOMA. DL1 is the weak (near) user while DL2 is the strong (far) user. IEEE 802.11a standard is implemented which is based on orthogonal frequency division multiplexing (OFDM) with fast Fourier transform (FFT) size of 64 and cyclic prefix (CP) is 16. IEEE 802.11a is chosen because its maximum transmit power is same as the USRP used in this demonstration which is +20 dBm. BS transmits a composite signal of binary phase shift keying (BPSK) and quadrature phase shift keying (QPSK) to DL1 and DL2 respectively at 2.45 GHz with 5 MHz bandwidth. UL user transmits QPSK modulated signal to BS at the same frequency, same bandwidth, and same time slot. The data transmission is in the form of packet in which each packet has short training field (STF) consisting of 2 OFDM symbols, long training field (LTF) consisting of 2 OFDM symbols, 1 SIGNAL field consisting of 1 OFDM symbol, and payload consisting of 30 OFDM symbols. STF is used for frame detection, and coarse timing and frequency offset estimation. LTF is used for fine timing and frequency offset estimation, and channel estimation. SIGNAL field consists the information about the decoding of payload. In this experiment 15 packets are transmitted in a burst. The LTF, STF, and SIGNAL field are BPSK modulated.
At the BS, the physical layer of IEEE 802.11a is implemented on Host-PC where the payload of each packet is generated as follows: the two sequences of transmitted bits are encoded by Bose-Chaudhuri-Hocquenghem (BCH) code of parameter n (block length) =15, k (number of parity check digits) =7, and t (error correcting bits) =2. Then, the first sequence of encoded bits is BPSK modulated followed by OFDM modulator with FFT size of 64 and CP of 16. The second sequence of encoded bits is QPSK modulated followed by OFDM modulator with FFT size of 64 and CP of 16. The two sequences after OFDM are scaled by α and combined to give one composite baseband signal. This baseband signal is sent to USRP using 10 gigabit Ethernet PCIe adapter card and SFP+ cable. The samples received by the USRP is converted to analog signal using DAC. It upconverts the signal to 2.45 GHz with I/Q rate of 5 MHz and is fed to the 2-way power splitter which is connected with the USRP as shown in the demo. One output of the power splitter is connected with antenna which transmits the signal over-the-air and another output is connected with the input of power combiner at the receiver of same BS USRP through fixed attenuator and cable.
At the BS receiver, the signal is received through two paths. One is through over-the-air and received by antenna at 2.45 GHz which is connected with one input of power combiner. Another input of power combiner at the receiver is connected with cable as shown in the demo. The length of the cable and the gain of the attenuator are adjusted such that the signals received at the inputs of power combiner should have equal strength and opposite phase: the output of the power combiner gives the SI cancelled signal after analog cancellation. The signal coming from the power combiner is fed to USRP where the signal is down converted to baseband and IQ samples are generated by using ADC which is then sent to the Host-PC. In the Host-PC, first the packet detection is performed by using STF followed by channel estimation and carrier frequency offset estimation (CFO) by using LTF. The channel estimation is performed before UL user's transmission and this estimated channel is used for decoding the remaining packets in the presence of UL user transmission. The CFO compensated samples are subtracted by the convolution of the estimated channel and the transmitted OFDM symbols, and the subtraction gives the residual SI. The receiver of BS is intended to receive the UL user transmitted signal and hence the residual SI acts as interference to the UL user communication.
For the UL user, transmit bits are encoded by BCH code of same parameter as used in BS transmission. Then the encoded bits are QPSK modulated followed by OFDM modulator. The baseband I/Q samples generated by OFDM modulator in Host-PC is sent to the USRP. The samples received by USRP is converted to analog signal using DAC, upconverted to 2.45 GHz with I/Q rate of 5 MHz. For DL2 user, the antenna receives the signal at 2.45 GHz and feeds to the USRP in which the signal is down converted to baseband and generates IQ samples by using ADC and sends to the Host-PC. The signal received by the DL2 user also contains DL1 user's signal and UL user's signal. The DL2 decodes its data by treating other signal as interference. Similarly, the signal received by DL1 user's signal is the combination of its own signal, DL2 user's signal and UL signal. Since the signal received by the DL1 user is dominated by DL2 user's signal, the DL1 user first decodes the DL2 user's signal and then performs SIC and finally decodes its own data.
